Verilog for Beginners

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Verilog for Beginners.

You will learn all basic and advance Verilog Topics..

Basic Verilog : Covers all information that a new user needs to build small Verilog models and run simulations..

Verilog HDL(Hardware description Language) offers many useful features..

Hierarchical modeling concept : Top-down and bottom-up design methodology.

Design Specification. Typical Design Flow. Behavioral Description.

There are two types of design methodologies : a top-down methodology and bottom-up design methodology..

Bottom-up methodology. Leaf cell. Leaf cell. Leaf cell.

The T Flip-flop shown in figure is made up of D flip-flop and exor gate..

Verilog Code : T-Flop Flop. module t_flip_flop ( T ,clk ,reset ,D);.

module d_flip_flop ( din ,clk ,reset ,dout );. output dout ;.

Number specification: sized and unsized.. Sized :.

Basic Concept : Number Specification. X or Z values :.

Verilog supports 4 state data types.. State Description 1 Logic 1, True condition 0 Logic 0, False condition X Unknown logic value Z High Impedance, floating state.

Nets : Keyword – wire. Nets represent connections between hardware elements..

Register : keyword – reg. Basic Concept : Data Types.

Example of Register. reg val_1; //declare a variable val_1 that can hold its value.

Vectors. Nets or reg data types can be declared as vectors (multiple bit widths)..

Vector Part select. We can select the parts of the vector..

Variable Vector Part Select. [<starting_bit>+:width] - part-select increments from starting bit.

We can use loop to select all bytes of the vector..

Integer. Integers are declared with keyword integer..

Real. Real numbers are declared with keyword real..

Time. A special time register data type is used in Verilog to store simulation time..

Arrays. Arrays are allowed in Verilog for reg, integer, time and real data types..

Values assignments to arrays:. integer cnt[0:7];.

Memory. Memories are modeled in Verilog simply as a one-dimensional array of registers..

Parameters. Verilog allows constants to be defined in a module by the keyword parameter..

String. String does not have any specific data type..

Special characters serve a special purpose in displaying strings, such as newline, tabs, and displaying argument values..

All system tasks appear in the form $<keyword>.. Operations such as displaying on the screen, monitoring values of signals, stopping, and finishing simulation are done by system tasks..

String Format Specifications. Format Display %d or %D Display in Decimal %b or %B Display in Binary %s or %S Display in string %h or %H Display in Hex %c or %C Display in ASCII character %m or %M Display hierarchical name %v or %V Display strength %o or %O Display in octal %t or %T Display in current time format %e or %E Display real number in scientific format %f or %F Display real number in decimal %g or %G Display real number in sci or dec..

Examples:. //Display value of 32-bit virtual address 3fe00abc at time 300.

$monitor. Verilog provides a mechanism to monitor a signal when its value changes..

Stopping and finishing in a simulation. $stop. Basic Concept : System Task.

All compiler directives are defined by using the ` construct..

`include. The `include directive allows you to include entire contents of a Verilog source file in another Verilog file during compilation..

End of the session. Hierarchical modeling concept : Top-down and bottom-up design methodology Basic concept : Number specification, data types, system tasks, compiler directives. Modules and ports : Module definition, Port declaration, Port connections. Gate level modeling : Modeling using basic Verilog gate primitives. Data flow modeling : Continuous assignment, delay specification, operators, Operands. Behavioral Modeling : Initial and always, blocking and non-blocking, generate, event and conditional statements, branching, loops, etc. Tasks and Functions. Useful modeling techniques..