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1Bahaa Radi, 1Md Mahadi Masnad,  1Jose Garcia Echeverria,  2Glenn Cowan, and 1Odile Liboiron-Ladouceur 1McGill University 2Concordia University  

TOWARDS MONOLITHICALLY INTEGRATED SIGE OPTICAL RECEIVER WITH AN ALL-SILICON PHOTODETECTOR 

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 Introduction and motivation Grating coupler and PD design Receiver design Conclusions   

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Explosive increase in data demand creates  a need for cheap, high-speed,  energy-efficient optical links. On the transmitter side VCSELs are used. On the receiver side, 850 nm photodetectors are  usually wire bonded to the receiver chip. This increases cost, and adds parastics due to this interconnet   potentially negatively impact performance.  Idea: Develop an efficient monolithic receiver that includes  an optimized 850 nm PD on the same chip of the receiver.   

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Top illuminated 850 nm all-si PDs suffer  from poor responsivity   because of silicon absorption. Idea: Using a grating coupler to direct  horizontally the light   increase optical absorption in the depletion region   improves responsivity.      

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Approximately 54% of the coupled  light is absorbed by the cone-shaped Si slab of the GC. The top cladding may only consist  of SiO2,or may also contain  a thin passivation layer of Si3N4 on top of the oxide layer  depends  on the foundry. This influences the tilt angle of the fiber array   determines the optimum grating period and fill factor.   

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For a top cladding made  of SiO2 only  max transmission at a fiber array tilt angle between 8o and 10o. with an extra passivation layer of Si3N4 on top,  a tilt angle near 20o is the optimal choice. 

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using the effective index of the grating with 120 nm etch depth,  the grating period is calculated   approximately 342 nm. The grating period to be  336 nm and 314 nm, while the optimum fill factors are  0.36 and 0.4 for top claddings with and  without Si3N4, respectively.  Avalanche gain = 6, 3-dB bandwidth = 16.4 GHz at 30 V reverse-bias voltage PD can support 64 Gb/s or 32 Gbaud   

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Receiver consists of: TIA: Converts current into voltage. common-emitter amplifier   followed by an emitter-follower stage.  Feedback resistor between the output of the emitter-follower and  the input of the common-emitter amplifier. A cascode amplifier for further amplification and  level shifting. A TIA replica. A differential pair for amplification   followed by emitter-follower stages. A DC offset compensation circuit   remove PD DC current to avoid saturating the amplifier.   

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Simulated AC response is shown  17 GHz 3-dB bandwidth   enough to support 32 Gd or 64 Gb/s Noise simulations  input-referred  current noise = 3.75 μA Indicates a sensitivity of 159 μAp-p for BER = 10-12.  Corresponding optical power = -8.7 dBm at the input of the all-silicon PD designed  in the previous section,  assuming a responsivity of 0.6 A/W.  

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Simulated eye diagram with a current of 159 μAp-p. The expected power consumption of the receiver is  168 mW  energy efficiency of 2.63 pJ/bit (excluding  the output buffer).  

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Optimized 850 nm PDs are  feasible in silicon stacks with the use of grating  couplers. Coupling efficiency of 54% and  a responsivity of 0.6 A/W was achieved. An energy efficiency receiver is  designed to leverage the designed PDs (2.63 pJ/bit ). The receiver achieves a bitrate of 64 Gb/s and  a sensitivity of -8.7 dBm. 

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The authors would like to thank  Lars Zimmermann and Georg Winzer from IHP Microelectronics for their helpful technical discussion regarding  the implementation of the proposed receiver. 

Towards Monolithically Integrated SiGe Optical Receiver with an All-Silicon Photodetector

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