TOPIC: Operating Systems Research for Reconfigurable Computing

TOPIC: Operating Systems Research for Reconfigurable Computing.

INTRODUCTION. From their original use as replacement components for discrete digital logic chips, field-programmable gate arrays (FPGAs) have transitioned through interesting and rapid role changes These changes have in turn driven changes in operating systems research as well. As in the past, future OS research in reconfigurable computing will continue to be influenced by change. In the early days of reconfigurable computing FPGAs were transistor-limited and rather simple..

Operating systems research started along two paths. Along the first path, the FPGA was used as an application accelerator. researchers recognized a unique potential of an FPGA: the ability to allow a portion of the chip to function while another portion was being reprogrammed. Along the second path, FPGAs were used to continue earlier explorations in the hardware/software codesign of real-time operating systems such as the VLSI scheduling coprocessor in the Spring kernel. The unveiling of a new class of devices called Platform FPGAs, circa 2000, proved pivotal for merging the two separate paths together.

'Ihese devices were introduced to compete in the growing systems-on-chip (SoC) market. • Much bigger than their predecessors, they included diffused blocks of hardware, including blocks of static RAM (SRAM) memory, multipliers, and programmable processors. 'Ihe programmable processor could now host an OS within the chip. The driving research question was how to extend the OS 's virtual machine model over the hardware/software 'Ihey defined new abstraction layers to allow hardware- resident threads to seamlessly interact with software threads transparently to the user..

Purpose. Create an environment that automatically generates a customized soft multiprocessor, given a set of architectural specifications Pipeline depth Unused instruction removal Interconnection network topology Inter-processor communication buffer sizing Investigate the effects of architectural optimizations on performance, area, and energy consumption across 8 stream-based computing benchmarks.

Soft Processor Architecture. 32-bit RISC architecture which implements a subset of MIPS instruction set architecture (ISA) Does not support: Caches Off-chip memory Branch prediction Exceptions Floating Point.

SPREE. Soft Processor Rapid Exploration Environment (SPREE) Used to generate individual soft processors within the system Generates synthesizable RTL from high-level architectural descriptions Configurable Pipeline Depth Appropriate data path/control for given ISA subset Includes communication FIFOs and interface logic Provides modified MIPS gcc compiler for generating binaries targeted for the customized processor.

Mesh vs. Point-to-Point Topologies. MESH TOPOLOGY Adjacent processors communicate directly with one another through FIFO buffer interface Non-Adjacent processor communication is achieved through a series of inter-processor hops Any given processor will use at most 8 unidirectional FIFOs (4 directions with separate FIFOs for read and write) POINT-TO-POINT TOPOLOGIES Source and destination processors communicate directly with one another o Some processors may have multiple input FIFOs while other may have none.

For FPGA-based heterogeneous multiprocessors, the choice of anywhere is vast and growing. Potential resources include different types of general-purpose, extensible, vector, and GPU processors, as well as custom hardware-based accelerators. Within an FPGA, the OS already has the opportunity to move these resources into and out of the hardware as if they were virtual pages being swapped into and out of a main memory. The move toward more self-awareness implies the OS may need more introspection or the ability to monitor itself as well as the applications and resources..

FPGAs are convenient for exploring new hardware/software codesigned runtime monitoring capabilities. 'Ihe successful outcomes of these types of research explorations may offer an altemate path to promoting architectural details up into the user code What forms of new abstractions and OS capabilities that might eventually evolve to support this type of self-aware and dynamic behavior is at this point speculation and hopefully motivation for others to join in on future research..

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