Project : Reduction of VDD3_ACC_DIG Failure Rate DMAIC - Story Board

Project : Reduction of VDD3_ACC_DIG Failure Rate DMAIC - Story Board.

Define Phase. Project “Reduction of VDD3_ACC_DIG Failure Rate“.

Terminal Pins VDD3 and VDD3_DIG are two independent voltage regulators that are used to supply the digital and analog blocks with 3.3V. This refers to the voltage level present at the VDD3 pin and is crucial for proper trimming of the device. An external capacitor is required to ensure stability of each regulator. During final testing, the voltage regulators were trimmed to 3.3 Volts to supply voltage VDD3 pins while maintaining a constant voltage..

undefined. Business Case. On the year 2023:. Project “Reduction of VDD3_ACC_DIG Failure Rate“.

Average rejection rate 4.10%. DEFINE: Supporting Data for Project Charter.

Sum of Final Test Yield 2023- January 2023-February 2023-March 2023- April 2023- May 2023-June 2023- July 2023- August 2023- September 2023- October 2023- November 2023- December 0.98643561458575135 0.92411924119241196 0.97099200190999169 0.97611645257773405 0.94201750241463078 0.94834325321231927 0.937409606810648 0.96195904592561654 0.95565283997399175 0.96178862335461046 0.93905777501340126 0.95416699803625282 Target Final Test Yield 2023- January 2023-February 2023-March 2023- April 2023- May 2023-June 2023- July 2023- August 2023- September 2023- October 2023- November 2023- December 0.96 0.96 0.96 0.96 0.96 0.96 0.96 0.96 0.96 0.96 0.96 0.96.

Project Team. Control. Improve. Analyse. Measure.

Measure Phase. Control. Improve. Analyse. Measure.

Data shows normal distribution with p value > 0.05..

VDD3 ACC DIG 3.8 3.7 3.6 3.5 3.2 IVDD3 DIG OVI vs start time IJPL LPL Marker by: (Row Num.. Color by: site + , 01 03 Shape by: (None) A1 values Size by: (None).

I Normal auantile Plot Histogram — VOD3 ACC "-value = 2814E-80 Marking: 110000 Marker by: ceor by Shape by: All 110000 DIG DIG OVI 3.20 Data table color by: V003 (b"ned).

Analyze Phase. Project Name. Control. Improve. Analyze.

Root - Cause - Diagram (Fish bone). Control. Improve.

Confirm Root Cause with Data. Control. Improve. Analyse.

Data Charts and Analysis : X1 : DEFECTIVE TESTER RESOURCES.

BAD OVI board. Data Charts and Analysis : X1 : DEFECTIVE TESTER RESOURCE:.

Advanced Box Plot 0, 301 33 113319 AM 2/11.2024 11:3207 2/11724 330:28 430:30 AM 2/11/2024 5M40xu 2'11,2024 41 4M COO' 2/112024.

Control. Improve. Analyse. Measure. Define. Next Steps/Quick Wins Load Board revision is not significant..

Control. Improve. Analyse. Measure. Next Steps/Quick Wins Load Board revision is not significant..

Output (Y) Data Type (Y) Input (X) Data Type (X) Graphical Tool Statistical Test Conclusion VDD_ACC_DIG__ Failure rate Continuous X1: DEFECTIVE TESTER RESOURCES Continuous HISTOGRAM 2-SAMPLE t 2-SAMPLE S.D Tester resource that wear out have significant variation in terms of measurements as compare to GOOD tester resource Continuous X2: DIFFERENT LOADBOARD REVISIONS Continuous HISTOGRAM 2-SAMPLE t 2-SAMPLE S.D Different LoadBoard revision have no significant variation is terms of measurement of VDD_ACC_DIG__.

Improve Phase. Control. Improve. Analyse. Measure.

Significant Factors (X’s) Potential Solutions X1 : Defective Tester Resources X1.1: Test program Debug : Avoid Auto ranging X1.2: Test program Debug : Trimming method.

Control. Improve. Analyse. Measure. Define. PLAN o.

Project “Reduction of VDD3_ACC_DIG Failure Rate“.

DO:. Test program debug activity done by TDEV Sir Guido: At routine VDD3DIG_Pretrimming Change the current range first before forcing the maxload current - According to TDEV’s recommendation, this prevents the force current and current range from being switched at the same time. Get back to 0 mA first before changing range As stated by TDEV, doing so will prevent "Auto-ranging," which occurs when the user does not define the range himself..

C) LTX Cadence Debugger (not connected) Eile Edit Senh Pyel Lools Pr«edt.re: Ed_if < 0.0 ) tim Ed_if > 0.0 ) set ovi ChM to fi FVDD301G_loa3 vmax SV •nin W yd-if 0 ) then: end_uhile wait( ) set ovi chm to fi SV vnin (N wait( 5CüÆ ) while nite ) end_if JAY to a bit the step of the LIO ( 33 ) md ( 64 ) ).

APPROVED BY TDEV. [image] Reply Reply All Tue Diane Cristine Cabrera RE: 50424-Brocap TP modification for 6sigma project T Esafat; c t Peter Pau catada Hi I agree with the changes and Guido's reconunendation regarding the OVI set-up, Also, MSA report is good, it didnt show any discrepancies on test parameters from the previous TP Thank you _.

BinName Pareto ainName SOFT Att UT Count 10425 7661 s Eus Frequenc... 31.70% 9.74% 7.18% 2.95% 081% 0.53% Cum Freq... 31.70% 64.74% 81.04% 84.03% 86.99% 89.78% 91.11% Current vs. Cumulative - AFE_SENS 4-TPOL RESP . 6 - PRE_CUTOFF... 9-100 THUT . 10 - 11 -VOD3 ACC o... Distribution — BinName AFE „ V003 ACC DIG _ AFE SENS uT . TPO RESP CUTOFF UT _ Cont •v•003 OIG MEG LPF IOO Showhide•_ ShowTop 10: (Wueaxi Color by ' (None) • All values _ TXOAC A.

Control. Improve. Analyse. Measure. Define. PLAN o.

On Wafer Sort, the same wafer sort Test program procedure on VDD3_DIG_OVI was used on both pre trimming and post trimming, but the wafer sort TP does not experience the over rejection that the Final Test TP has..