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[Audio] In my presentation I will tell you about the Cache Coherence Problem and its solutions..

[Audio] Caching instructions and data is needed to reduce the average access latency. However caching shared data causes a problem, which is called Cache Coherence Problem. In a multiprocessor system, all the processors in the system share the main memory via a bus. For higher performance each processor implements its own cache. Cache coherence refers to the problem of keeping the data in these caches consistent. The main problem is dealing with writes by a processor. Let me illustrate it. In a multi-processor system every core has its own independent memory storage, also there are some memory storages which are shared among all of them. Here we have four different processors, namely P1, P2, P3 and P4. All these processors have their own private caches. The shared storage is the main memory, which is connected with the processor with the help of the system bus. Additionally all the different private caches they are interconnected with the help of the internal bus. Now suppose that inside the main memory we have a program code which has a global variable a and that has been initialized to 18. Consider that all these processors operate on the same data. For example P1 wants to read A. It looks for the value inside its private cache. Since A is not there it will incur a cache miss and fetch the value of A from the main memory into its private cache. Now processor P3 wants to perform the operation A plus 2 and to do this it reads A. A is also not in the private cache of P3 and P3 also fetches A from the main memory into its private cache. Now it can execute the operation and increment the value of A by two. So it writes a new value to it, which is 20, but we have write back so the value is written only to the cache of P3. Now there are three copies of A – one in the main memory, one in the private cache of P1 and one in the private cache of P3. But they are no longer coherent, they are no longer the same. And when for example processor 1 reads A it will read the old value 18 which is wrong since A has gotten a new value. And this problem is the cache coherence problem. So the Cache Coherence Problem is the challenge of keeping multiple local caches synchronized when one of the processors updates its local copy of data which is shared among multiple caches..

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