Name: 8086 MICROPROCESSOR- PIN DIAGRAM
Uploaded: 2022-04-17
Duration: 5 min 5 s
Description: A modern vector representation with the blue element.

A modern vector representation with the blue element. 

Scene 1

A modern vector representation with the blue element

8086 MICROPROCESSOR-           PIN DIAGRAM

Timeline Description automatically generated. 

Scene 2

Timeline

Description automatically generated

A picture containing snow, outdoor Description automatically generated. 

Scene 3

A picture containing snow, outdoor

Description automatically generated

AD0-AD15( Address /Data bus):                                                                                     These are low order address bus. They are multiplexed with data. When AD lines are used to transmit memory address the symbol A is used instead of AD, for example A0-A15. When data are transmitted over AD lines the symbol D is used in place of AD, for example D0-D7, D8-D15 or D0-D15.

A picture containing text, stationary, envelope Description automatically generated. 

Scene 4

A picture containing text, stationary, envelope

Description automatically generated

S2, S1, S0:                          These status pins are used by the 8288  bus controller for generating all the memory and I/O operation and access control signals.

A16-A19:                                            High order address bus. These are multiplexed with status signals.

A picture containing text, envelope, businesscard Description automatically generated. 

Scene 5

A picture containing text, envelope, businesscard

Description automatically generated

A16/S3, A17/S4, A18/S5, A19/S6:                                                                            The specified address lines are multiplexed with corresponding status signals.

BHE’/S7(Bus High Enable/Status):                                                                                            It is used to enable data onto the most significant half of data bus(D8-D15). A  8- bit device connected to upper half of the data bus use BHE (Active Low) signal. It is multiplexed with status signal S7.

Scene 6

RD:                       This is used for read operation. It is an output signal.

READY :                                    This is the acknowledgement from the memory or slow device that they have completed the data transfer. The signal made available by the devices is synchronized by the 8284A clock generator to provide ready input to the microprocessor.

INTR(Interrupt Request): This is sampled during the last clock cycles of each instruction for determining the availability of the request. If any interrupt request is found pending, the processor enters the interrupt acknowledge cycle.. 

Scene 7

INTR(Interrupt Request):                                                                       This is sampled during the last clock cycles of each instruction for determining the availability of the request. If any interrupt request is found pending, the processor enters the interrupt acknowledge cycle.

A picture containing text, businesscard Description automatically generated. 

Scene 8

A picture containing text, businesscard

Description automatically generated

NMI(Non maskable interrupt):                                                                           NMI is non-maskable internally by software. This is an edge triggered input which results in a type II  interrupt.This  input has been synchronized internally.

INTA(Interrupt acknowledge):                                                                          It is active low(0) during T2, T3 and Tw of each interrupt acknowledge cycle.

A picture containing text, whiteboard Description automatically generated. 

Scene 9

A picture containing text, whiteboard

Description automatically generated

RQ’/GT1′, RQ’/GT0′(Request/Grant):                                                                                              These pins are used by local bus masters used to force the microprocessor to release the local bus at the end of the microprocessor’s current bus cycle. Each of the pin is bi-directional. RQ’/GT0′ have higher priority than RQ’/GT1′.

Scene 10

LOCK’ :                                 It indicates that other system bus masters have not been allowed to gain control of the system bus while LOCK’ is active low(0). The LOCK signal will be active until the completion of the next instruction.

TEST’ :                                  This examined by a ‘WAIT’ instruction. If the TEST pin goes low(0), execution will continue, else the processor remains in an idle state.

Scene 11

CLK(Clock Input):                                                          The clock input provides the basic timing for processing operation and bus control activity.

RESET :                         This pin requires the microprocessor to terminate its present activity immediately. The signal must be active high(1) for at least four clock cycles.

Scene 12

Vcc  :                           Power Supply( +5V D.C.)

GND :                                  Ground

QS1,QS0(Queue Status):                                                          These signals indicate the status of the internal 8086 instruction queue.

Text Description automatically generated. 

8086 MICROPROCESSOR- PIN DIAGRAM

Scene 1 (0s)

Scene 2 (19s)

Scene 3 (26s)

Scene 4 (56s)

Scene 5 (1m 20s)

Scene 6 (2m 0s)

Scene 7 (2m 21s)

Scene 8 (2m 44s)

Scene 9 (3m 17s)

Scene 10 (3m 47s)

Scene 11 (4m 9s)

Scene 12 (4m 32s)

Scene 13 (4m 52s)